(1) Field of the Invention
In its generality, the invention relates to phase-locked loops and more specifically to a phase-locked loop whose phase detector is in the form of a multiplying circuit.
(2) Description of the Prior Art
As is generally known, a phase-locked loop is a circuit comprising a voltage-controlled oscillator (VCO) which is controlled by a control voltage and produces an output signal whose frequency is determined by this control voltage. In the foregoing, the output signal of the voltage-controlled oscillator will be denoted the VCO-signal for the sake of brevity, and its frequency the VCO-frequency. The control voltage is generated by a cascade-arrangement of a phase detector and a low-pass filter. A reference signal having a predetermined reference frequency and a comparison signal having a predetermined comparison frequency are applied to this phase detector.
The reference signal may be a signal produced by a reference source, for example a crystal oscillator. It may alternatively be a pilot signal present in a received signal. The comparison signal is derived from the VCO-signal. If the loop is locked, then the frequency of the comparison signal is equal to the reference frequency and there is no phase difference, or only a very small one between the comparison signal and the reference signal. Any change in the frequency or the phase of the comparison signal relative to the reference signal causes the control voltage to change, as a result of which the frequency of the VCO-signal changes such that the frequency difference and also any phase difference between the reference and comparison signals is eliminated.
In the generally known analogue phase-locked loop, a voltage-controlled oscillator is used which produces a, usually sinusoidal, analogue VCO-signal. The reference signal is then also an analogue signal. In this analogue phase-locked loop it can be determined at any instant whether there is a phase difference between the comparison signal and the reference signal. If so, the VCO-frequency is immediately corrected.
In a digital phase-locked loop the comparison signal is a binary pulse-shaped signal and this usually also holds for the reference signal. This comparison signal is derived with the aid of a digital frequency divider circuit from the voltage-controlled oscillator which oscillates at a frequency which is significantly higher than the reference frequency. The stability of the voltage-controlled oscillator is considerably poorer in this digital phase-locked loop than in the analogue phase-locked loop. This is caused by the frequency divider circuit. If, for example, this frequency divider circuit has a dividing factor R, then a correction of the VCO-frequency is effected not more than twice per R periods of the VCO-signal, as the comparison signal only changes its value twice in each group of R VCO-signal periods. The oscillator can in principle oscillate at any frequency during two consecutive corrections.
Another embodiment of a phase-locked loop is extensively described in the Reference (see paragraph C). More specifically, in the phase-locked loop described therein the phase detector is in the form of a multiplier circuit having a multiplier to which an analogue reference signal is applied and also a sampled version of an analogue comparison signal. The frequency of this analogue comparison signal is equal to the reference frequency and sampling has been effected under the control of clock pulses occurring at a rate which is a multiple N of the comparison frequency. These clock pulses are produced by the voltage-controlled oscillator which is in the form of a clock pulse oscillator.
In a practical embodiment, the multiplier circuit comprises a pulse distributor circuit receiving the clock pulses and distributing them cyclically over not more than N distributor outputs. More specifically, the N.sup.th clock pulse is applied to the distributor output having number n modulo N, or, which is the same, the distributor output having number k receives the clock pulses having the numbers k+iN, where i=. . . -2, -1, 0, 1, 2, 3, . . . . Thus, a sequence of main control pulses is produced at each of these distributor outputs. In addition, a plurality of signal channels are present which each receive the reference signal and each comprise a cascade arrangement of a switching circuit and a weighting network having a constant weighting factor. The value of the weighting factor of the weighting network in the k.sup.th signal channel is related to the value of the comparison signal at the instant at which the clock pulses having number k+iN occur; i=. . . -2, -1, 0, 1, 2, 3, . . . . In other words, the weighting factor is proportional to a given sample of the comparison signal. Each switching circuit is controlled by one or more of said sequences of main control pulses. The signal channel produces a main signal for each sequence of main control pulses applied to the relevant switching circuit. In an adder arrangement all the main signals are added together which produces the desired product signal.
In this prior art multiplying circuit the desired dividing factor of the phase-locked loop is also incorporated; it is namely proportional to the number of sequences of main control pulses produced by the pulse distributor circuit.
As in this embodiment of the phase-controlled loop a sample of the comparison signal is applied to the multiplier for each clock pulse, it is also possible to correct the frequency of the clock pulse oscillator at any clock instant, so that the clock pulse oscillator now has a significantly higher stability than the oscillator in the digital phase-locked loop. However, because of the absence of an adjustable frequency divider circuit it is less flexible than this digital phase-locked loop.